דווקא את ה-42 הצלחתי להבין הם הגדירו T0 כמשך זמן בו אות השעון 0 ו-T1 כמשך הזמן בו אות השעון 1. ולכן Tclk=T0+T1. ואז לוקחים חיתוך ויוצא
Tclk=max{36,25+19}=42
אבל אני לא לגמרי מצליח להבין איך זה מסתדר עם ההגדרות שראיתי (באתר הזה):
http://6004.mit.edu/Fall13/tutprobs/state03.gif
QST
Rewrite the timing specifications for the system as a whole taking into account d1 and d2. Don't make any assumption about the
relative sizes of the two delays.
ANS
The delay d1 causes all timing specifications associated with register R1 to be shifted later in time by d1. Likewise the delay d2 causes all timing specifications associated with register R2 to be shifted later in time by d2. Note that we still use the original clock signal as our reference for the system, so the setup times for the registers R1 and R2 become shorter by d1 and d2, respectively, and the hold times for R1 and R2 become longer by d1 and d2.
:The timing specifications of the system, taking d1 and d2 into account, are
tS = tPD,CL1 + tS,R1 - d1 = 6 - d1
tH = tH,R1 - tCD,CL1 + d1 = 1 + d1
tCD = tCD,R2 + d2 = 2 + d2
tPD = tPD,R2 + d2 = 8 + d2
Finally,
(פה הם לוקחים כבר ערכים חדשים של FF2 FF1)
tCLK >= tPD,R1 + tPD,CL2 + tS,R2
tCLK >= 2 + d1 + 5 + 4 - d2
tCLK >= 11 + d1 - d2
או שאין קשר בין התרגילים?